Digital Neural Emulators Using Tree Accumulation and Communication Structures

Abstract

This paper proposes three digital artificial neural network processors suitable for the emulation of fully interconnected neural networks. The processors use N2 multipliers and an arrangement of tree structures that provide the communication and accumulation function either individually or in a combined manner using communicating adder trees. The first digital neural emulator connects N2 multipliers by two sets of communicating adder trees and 2N neuron activation functions with a neuron value switching control mechanism that is used in association with the communicating adder trees to accomplish the N by N communications. The second digital neural emulator utilizes N2 multipliers, N accumulation trees, N neuron activation functions, and N communication trees, and the third emulator connects N2 multipliers by one set of N communicating adder trees and N sigmoid generators, and uses a novel neuron value path switch to accomplish the N by N communications. The performance for the emulation of an N-neuron network for all processors is achieved in 2 log2 N + C time units, where C is a constant equal to the multiplication, neuron activation, and internal fixed delays. The feasibility and characteristics of the proposed configurations to emulate single and/or multiple neural networks simultaneously are also discussed and a comparison with recently proposed neurocomputer architectures is reported. © 1992 IEEE