Endurance-aware cache line management for non-volatile caches

Abstract

Nonvolatile memories (NVMs) have the potential to replace low-level SRAM or eDRAM on-chip caches because NVMs save standby power and provide large cache capacity. However, limited write endurance is a common problem for NVM technologies, and today's cache management might result in unbalanced cache write traffic, causing heavily written cache blocks to fail much earlier than others. Although wear-leveling techniques for NVM-based main memories exist, we cannot simply apply them to NVM-based caches. This is because cache writes have intraset variations as well as interset variations, while writes to main memories only have interset variations. To solve this problem, we propose i 2WAP, a new cache management policy that can reduce both inter-and intraset write variations. i2WAP has two features: Swap-Shift, an enhancement based on existing main memory wear leveling to reduce cache interset write variations, and Probabilistic Set Line Flush, a novel technique to reduce cache intraset write variations. Implementing i2WAP only needs two global counters and two global registers. In one of our studies, i 2WAP can improve the NVM cache lifetime by 75% on average and up to 224%. We also validate that i2WAP is effective in systems with different cache configurations and workloads. © 2014 ACM.