Functional verification and the physical design of MIPS architecture

Abstract

The Microprocessor with no Interlocked Pipeline Stages (MIPS) is Reduced Instruction Set Computation (RISC) based architecture. The RISC is composed of a smallest set of instructions for increasing the speed processor. In this work, functional verification and physical design of the 32-bit 5-stage pipelined MIPS processor is proposed to be done. Here, the physical design is aimed to improve the area, power and speed performance of the design. Cadence SOC encounter is proposed to use for the physical design of the MIPS architecture. Also, this work explores the complete the ASIC flow from RTL to GDSII for MIPS processor using TSMC (Taiwan semiconductor Manufacture Company) 90nm technology. Finally, performance of the proposed implementation will be compared with the existing implementations.