Journal Article

A time-multiplexed reconfigurable neuroprocessor

IEEE Micro (1997) 17(1) 58-65
DOI: 10.1109/40.566208
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Abstract

For efficient chip area use and operating speed, this multilayered pulse stream neuroprocessor design uses a mixed analog-digital implementation.

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APA

Sibai, F. N., & Kulkarni, S. D. (1997). A time-multiplexed reconfigurable neuroprocessor. IEEE Micro, 17(1), 58–65. https://doi.org/10.1109/40.566208

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