A low noise amplifier co-designed with ESD protection circuit in 65-nm CMOS

Abstract

By means of co-design ESD protection circuit as the low noise amplifier (LNA) input matching network, a 5.8-GHz LNA with excellent ESD and noise performances is demonstrated by a 65-nm CMOS technology. The diode-based ESD design with a power clamp can achieve 4 kV human body model (HBM) performance while the noise figure (NF) is only 0.05 dB higher than that of the LNA without the extra ESD blocks. Under a supply voltage of 1.2 V and drain current of 7 mA, the ESD-LNA has a NF of 1.9 dB with an associated power gain of 18 dB. The input third-order intercept point (IIP3) is -11 dBm and the input and output insertion losses are below -16 dB and -20 dB, respectively. © 2009 IEEE.