Analysis of Clock trees for optimization through Multi point Clock Tree Synthesis

Abstract

With rapid development of deep submicron (DSM) VLSI circuits design, building clock tree with minimal insertion delays and minimal skews has turned out to be challenging. In this Paper for a given specified block with a latency of 530 ns it is aimed to achieve a latency of 400ns and achieve optimal power. Here a Clock Tree Synthesis method is used to reduce the latency and obtain the timing closure for the given block. The analysis is made and compared in terms of clock skew and insertion delay by varying the tap points. In this process of achieving the timing closure it is observed power has optimized by selecting the appropriate tap points.