A Diagonal Active-Area Stacked Capacitor Dram Cell With Storage Capacitor On Bit Line

Abstract

A new stacked-capacitor (STC) cell concept for 16-Mbit DRAM's is introduced. The new STC cell features a storage capacitor placed on a bit line and a diagonal active area. This enables a large storage capacitance, 35 fF/bit, to be achieved on a small cell size of 3.36 μm 2. By eliminating completely the structural interferences between bit line and plate electrode, the storage-node pattern is maximized. The new STC cell also features low noise characteristics due to its shielded bit-line structure. This minimizes the interbit-line capacitance to below 1 percent of the bit-line capacitance in the memory array. The average charge retention time, measured using an experimental 2-kbit array, is determined to be 30 s at 40°C. The characteristics of the diagonal active memory cell transistor are comparable to those of a conventional transistor. © 1990 IEEE