ATTC (@) : Addressable-TLB based translation coherence

Abstract

Heterogeneous memory systems are getting popular, however theyface significant challenges from translation coherence overheadsfrom page remappings. Translation coherence, which is typicallyimplemented in software, can consume up to 50% of the runtime forsome applications in virtualized platforms. In this paper, we proposeATTC Addressable TLB-based Translation Coherence, a hardwaretranslation coherence scheme which eliminates almost all of theoverheads associated with software-based coherence mechanisms,and overcomes the challenges in existing hardware schemes. Unlikeother proposals (HATRIC, UNITD) that require on-chip TLB tagsto enforce coherence and are capable of tracking only the lastlevel page table entries of either the guest or host page tables,ATTC tracks changes to both guest and host page tables withoutrequiring any additional metadata in L1, L2 TLBs. ATTC enforces a"point of coherence"uniformly for both guest and host page tableupdates using an addressable TLB (ATLB) in the DRAM akin tothe one in [41]. An inverse mapping table (present inDRAM) that maps host physical pages to ATLB locations helps toprecisely track translations. We study the proposed ATTC schemein detail for an emerging hybrid memory organization (a mix ofDRAM and NVM) and show that ATTC practically eliminates alltranslation coherence overheads, yielding an average improvementof 35.7% over a baseline software coherence scheme in virtualizedenvironment and 7.4% over the hardware HATRIC scheme.