READ-Optimized 28nm HKMG Multibit FeFET Synapses for Inference-Engine Applications

Abstract

This paper reports 2bits/cell ferroelectric FET (FeFET) devices with 500 ns write pulse of maximum amplitude 4.5V for inference-engine applications. FeFET devices were fabricated using GlobalFoundries 28nm high-k-metal-gate (HKMG) process flow on a 300mm wafer. The devices were characterized, and statistical modeling of variations in the fabricated devices was carried out based on experimental data. Furthermore, the model was applied to multi-layer perceptron (MLP) neural network (NN) simulations using the CIMulator software platform. The neural network (NN) was trained offline, and the weights were transferred to the synaptic devices for an inference-only operation. Device-to-device (D2D) and cycle-to-cycle (C2C) variations are limited by optimal process conditions and do not impact inference accuracy. However, due to short-term retention, read-to-read (R2R) variation significantly affects inference operation. This work proposes a synergistic READ-optimization approach to mitigate the impact of short-term retention and device variation issues. The optimization technique fostered immunity in the MLP-NN towards R2R variations, and the MLP-NN maintains inference accuracy of 97.01%, while the software baseline is 98%.