Cascaded H-bridge multilevel inverter

Abstract

This paper Presents design and simulation of a cascade H bridge multilevel inverter using sinusoidal pulse width modulation technique. The purpose of multilevel inverter is to generate stair case sinusoidal pulse using different DC Supply. In this paper we generate carrier based SPWM scheme using PD, POD, APOD compare it for five level and seven level by doing FFT analysis in order to find optimized output voltage quality. The MATLAB, Simulink result shows that seven level inverter voltages has less total harmonic distortion in comparison with five level inverter.