A low-voltage CMOS MIN circuit with 3N+1 complexity and 10 mV/10 ns corner error

Abstract

An 1.5 V CMOS voltage-mode MIN circuit with 3N + 1 complexity and 10 mV/10 ns corner error is presented. The proposed approach uses a low impedance configuration to operate with low voltage supply requirements and without the need of low-voltage techniques with large area requirements. The basic cell and a LTA circuit prototype were simulated, fabricated and characterized using a double poly, three metal layers 0.5 μm CMOS technology from ON SEMI foundry. © IEICE 2013.