Design and Comparison of 8x8 Wallace Tree Multiplier using CMOS and GDI Technology

Abstract

Multiplier is an important building block in the design of digital circuits. Multiplier is widely used in Digital signal processing and in communication applications. Compact and small circuit with low power dissipation and very small delay are main desire of circuit designer in the field of VLSI design. A Wallace tree multiplier is an example of improved version of tree base multiplier. Many algorithms have been introduced in the search of the fastest multiplier. There are different types of multiplier based on the algorithm and Wallace tree multiplier is one of them. It uses carry save addition algorithm.The result shows that the GDI based Wallace tree multiplier is performing best as compare to CMOS based multiplier. Power dissipation and delay of GDI and CMOS based Wallace tree multiplier at 1.8 V power supply is 8.8mW and9.6mW and 0.02nS & 0.17nS respectively