Comprehensive Analysis of Source and Drain Recess Depth Variations on Silicon Nanosheet FETs for Sub 5-nm Node SoC Application

Abstract

Excess source and drain (S/D) recess depth ( $T_{SD}$ ) variations were analyzed comprehensively as one of the most critical factors to DC/AC performances of sub 5-nm node Si-Nanosheet (NS) FETs for system-on-chip (SoC) applications. Variations of off-, on-state currents ( $I_{off}$ , $I_{on}$ ) in three-stacked NS channels and parasitic bottom transistor ( $tr_{pbt}$ ), gate capacitance ( $C_{gg}$ ), intrinsic switching delay time ( $\tau _{d}$ ), and static power dissipation ( $P_{static}$ ) are investigated quantitatively according to the $T_{SD}$ variations. More S/D dopants diffuse into the $tr_{pbt}$ with the deeper $T_{SD}$ , so the $I_{off}$ and $I_{on}$ increase due to raised current flowing through the $tr_{pbt}$. Especially, the $I_{off}$ of PFETs remarkably increases above the certain $T_{SD}$ ( $T_{SD,critical}$ ) compared to NFETs. Furthermore, the $I_{on}$ contribution of each channels having the $T_{SD,critical}$ is the largest at the top NS channel and the $tr_{pbt}$ has the ignorable $I_{on}$ contribution. Among the NS channels, the top (bottom) NS channel has the largest (smallest) $I_{on}$ contribution due to its larger (smaller) carrier density and velocity for both P-/NFETs. The $C_{gg}$ also increases with the deeper $T_{SD}$ by increasing parasitic capacitance, but fortunately, the $\tau _{d}$ decreases simultaneously due to the larger increasing rate of the $I_{on}$ than that of the $C_{gg}$ for all SoC applications. However, the $P_{static}$ enormously increases with the deeper $T_{SD}$ , and low power application is the most sensitive to the $T_{SD}$ variations among the SoC applications. Comprehensive analysis of the inevitable $tr_{pbt}$ effects on DC/AC performances is one of the most critical indicators whether Si-NSFETs could be adopted to the sub 5-nm node CMOS technology.