Design of low power 8T SRAM array with enhanced RNM

Abstract

The paper discusses about the power reduction techniques in a memory cell. Two commonly used SRAM cells, 6T and 8T SRAM are compared in terms of their stability and power gating and MTCMOS technique is implemented to observe power reduction. 8T SRAM cell proves to be more reliable and stable as this has decoupled read and write control paths. The 8T SRAM cell is optimized for better RNM and an array of 4x8 bit cell is constructed with proposed 8T cell. The array with the MTCMOS technique used in the decoder proves 6.9 % power reduction than the circuit without the MTCMOS technique. The 32-bit cell array is constructed with gpdk 180 and consists of 8 write driver circuit, 8 precharge circuit and 8 sense amplifier along with 2:4 decoder and 32 SRAM cells.