Deposited ALD SiO 2 High-k/Metal Gate Interface for High Voltage Analog and I/O Devices on Next Generation Alternative Channels and FINFET Device Structures

Abstract

A highly reliable SiO 2 deposited by atomic layer deposition (ALD) as a gate dielectric interface layer with high-k/metal gate (HKMG) in high voltage I/O field effect transistor (FETs) for advanced technologies has been demonstrated. Improved process control, better gate oxide conformality, superior dielectric reliability (over CVD SiO 2 ), and equivalent uniformity and reliability compared to thermal oxide proves its usefulness for FinFET/ETSOI I/O devices. In addition, use of ALD SiO 2 with novel interface layer results in reduced interfacial regrowth on SiGe channel, which when coupled with post deposition nitridation and annealing optimization for optimal performance, is an attractive oxide optimization option for alternate channel architectures.