Test generation for open defects in CMOS circuits

Abstract

Open defects in CMOS circuits require two-pattern tests for detection. Traditionally, the only two-pattern tests included in manufacturing test are those targeting transition delay faults. Such tests, however, do not provide complete coverage of all the open defects. In this paper we propose the use of a unified test set that detects all inline resistance faults which model interconnect open defects and all transistor stuck-open faults which model intra-gate open defects in order to obtain a comprehensive coverage of open defects. We also describe a method of generating the proposed test set using an ATPG program for transition delay faults whose sizes are comparable to transition delay fault based test set. © 2006 IEEE.