Evaluating the Statistical Stability of POSIT Arithmetic and IEEE 754 Float to Accelerate Data for Detection of Breast Cancer

Abstract

In recent years, the researcher has focused on the hardware implementation of Floating Point Units (FPUs), which have a huge area and energy footprint. Due to their greater accuracy, speed, and simpler hardware design, Posit Arithmetic Units (PAUs) are proposed to replace IEEE 754-2008 compliant FPUs. It is important to improve existing floating-point IP cores for field-programmable gate array (FPGA) based applications. In comparison with other floating-point formats, posits number representation offers greater dynamic range and numerical accuracy. Various researchers attempted to implement a support vector machine (SVM) using hardware implemented on FPGA platforms to achieve high performance at lower power consumption and cost. As a result, the algorithm is unsuitable for embedded real-time applications. Therefore, SVM linear classifier is implemented on hardware, decreasing the latency and executing the task in real-time. This paper proposes an SVM linear classifier with pipeline architecture for fast processing in Verilog HDL using a single-precision IEEE standard 754 number format with 32-bit representation. The POSIT algorithm design is done with 24-bit representation using a software approach to determine the accuracy of prediction for the detection of Breast Cancer. The accuracy rate is computed both using software and hardware for performance evaluation. The pipelined SVM architecture is designed using Verilog HDL and synthesized using the Vivado simulation tool. The design is configured to the Xilinx KC705 Kintex-7 evaluation board for implementation.