An Adjustable Gate Driver Based on the Optimization of Switching Transient Performances

Abstract

An adjustable gate driver is proposed based on the optimization of switching transient performances. The turn-on process is optimized through an adjustable charging current, while the turn-off process is optimized through an adjustable segmented drive current. The proposed gate drive circuit has the advantage of reducing switching loss, delay, and total switching time, while maintaining the switching stress and EMI noise level during both turn-on and turn-off transients. The proposed driver can be integrated into gate driver ICs, and the switching performance can be externally adjusted to match the power device for different applications. By combining the above techniques, an adjustable gate driver IC has been developed using the 0.25~μ m BCD process. The simulated and experimental results validate the proposed technique. Compared to the conventional gate driver, the overshoot voltage has been reduced from 15.4% to 8.3%, and the overshoot current has decreased from 20.5% to 10.2% under a 10A load condition.