Abstract
Value prediction attempts to eliminate true-data dependencies by dynamically predicting the outcome values of instructions and executing true-data dependent instructions based on that prediction. In this paper we attempt to understand the limitations of using this paradigm in realistic machines. We show that the instruction-fetch bandwidth and the issue rate have a very significant impact on the efficiency of value prediction. In addition, we study how recent techniques to improve the instruction-fetch rate affect the efficiency of value prediction and its hardware organization.
Cite
CITATION STYLE
Gabbay, F., & Mendelson, A. (1998). Effect of instruction fetch bandwidth on value prediction. In Conference Proceedings - Annual International Symposium on Computer Architecture, ISCA (pp. 272–281). IEEE Comp Soc. https://doi.org/10.1145/279361.278058
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