Influence of High-k Gate Dielectric on Nanoscale DG-MOSFET

Abstract

Influence of dielectric materials as gate oxide on various short channel device parameters using a 2-D device simulator has been studied in this paper. It is found that the use of high-k dielectrics directly on the silicon wafer would degrade the performance. This degradation is mainly due to the fringing field effect developed from gate to source/drain. This fringing field will further generate electric field into the channel region from source/drain region which weakens the gate control. Therefore, by taking the gate stack engineering into account it has been shown that the induced electric field along the channel can be minimized as well as the device performance can be enhanced. This paper examined various parameters of the device like potential distribution from source and drain, threshold voltage (V th), drain induced barrier lowering (DIBL), subthreshold slope (SS), on-current (I on), off-current (I off) and Transconductance (g m) by taking different dielectric materials [SiO 2 (=3.9), Si 3 N 4 (=7.5), HfO 2 (=24) and Ta 2 O 5 (=50) ] as gate oxide (s).