Area–time–energy efficient architecture of CBNS-based fast Fourier transform

Abstract

A new approach for implementing the fast Fourier transform (FFT) using complex binary number system (CBNS) is presented in this paper. The advantage of using CBNS is that instead of processing the real and imaginary parts of a complex number separately, we can process both as a single entity. A total of four FFT architectures have been developed, which are 16-, 64-, 256-, and 1024-point FFT architectures. The proposed FFT is designed using Verilog-HDL and implemented using a Virtex-7 field-programmable gate array (FPGA). The maximum clock rate achieved by the proposed FPGA-based design is 376.1 MHz. The FPGA resource utilization of the FFT is less than the state-of-the-art FFT designs. An application-specific integrated circuit (ASIC) for the FFT is also designed. The normalized energy per FFT of the proposed ASIC is 0.14 nJ, and the normalized area per FFT of the ASIC is 1.08 mm2 which is less than other existing designs.