FPGA design considerations in the implementation of a fixed-throughput sphere decoder for MIMO systems

Abstract

A field-programmable gate array (FPGA) implementation of a new detection algorithm for uncoded multiple inputmultiple output (MIMO) systems based on the complex version of the sphere decoder (SD) is presented in this paper. It achieves quasi-maximum likelihood (ML) performance in systems where a hardware implementation of the maximum likelihood detector (MLD) is unfeasible due to its high complexity. It achieves this with a highly parallel and fully pipelined architecture. In addition, different design modifications are proposed and implemented to reduce the resource use and/or increase the throughput of the algorithm. © 2006 IEEE.