Effect of well and substrate parameters on the latchup degradation of CMOS structures during e-beam voltage contrast measurements

Abstract

This paper relates to the contactless testing of Complementary Metal Oxide Semiconductor (CMOS) structures. It points out experimental data showing a degradation in the latchup immunity during standard e-beam voltage contrast testing. It emphasizes the phenomenon of charge deposition on the oxide and a lost of reliability related to well and substrate parameter values. The experiments have been carried out in a classical Scanning Electron Microscope (SEM) on 2 μm, epitaxial, CMOS test vehicles. An electrical model is used to explain the results.