FPGA implementation of fault tolerant full adder design for high speed VLSI architectures

Abstract

The essential goal is to distinguish and diminish the deficiencies in full Adder configuration making use of Self checking and Self Repairing Adder Block. The tempo of chip disappointment is straightforwardly relative to chip thickness. A framework should be flaw tolerant to diminish the frustration rate. The nearness of different troubles can demolish the usefulness of complete snake. This paper displays a region proficient flaw tolerant complete snake shape that may repair issues without interfering with the everyday assignment of a framework. The combo and duplicate is finished through way of making use of Xilinx ISE 14.7 and actualized on FPGA Spartan three..