TAIR: Testability analysis by implication reasoning

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Abstract

To predict the difficulty of testing a wire stuck-at fault, testability analysis algorithms provide an estimated testability value by computing controllability and observability. In most common previous work such as COP and SCOAP, signal correlation between controllability and observability is not well handled. As a result, the estimated values can be quite inaccurate. On the other hand, some previous work can take into account signal correlation but may require more CPU time. This paper discusses an efficient method for testability analysis improvement. Our algorithm starts with results obtained from conventional testability analysis such as COP. For each stuck- at fault, we gradually refine these results by recursively applying some simple signal correlation rules. Experimental results show that, with reasonable run-time overhead, significant improvement for testability analysis can be achieved.

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Chang, S. C., Jone, W. B., & Chang, S. S. (2000). TAIR: Testability analysis by implication reasoning. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 19(1), 152–160. https://doi.org/10.1109/43.822627

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