Achieving Ultrahigh Threshold Voltage in Enhancement-Mode AlGaN/GaN HEMTs With an AlxTiyO/p-GaN Integrated Gate Stack—Part II

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Abstract

This work proposes and demonstrates a novel gate stack design for enhancement-mode (e-mode) AlGaN/GaN HEMTs to achieve a significantly increased threshold voltage (VTH ~ 4.2 V). The design features an AlTiO dielectric layer atop a p-GaN/AlGaN/GaN heterostructure, allowing VTH control through various gate stack parameters. Detailed experiments and simulations show that VTH tuning is governed by: 1) p-GaN thickness and doping; 2) leakage characteristics; 3) dielectric crystalline quality; 4) dielectric constant; and 5) the p-type properties of AlTiO. High-resolution TEM (HRTEM) analysis, C–V/I–V analysis, and TCAD computations revealed an interdependence between microcrystalline disorder, leakage, and dielectric constant. Suppressing leakage by reducing the microcrystalline order of AlTiO enables a turn-on mechanism dominated by p-GaN hole depletion, thereby increasing VTH. Additionally, increased disorder lowers the dielectric constant. This results in a higher voltage drop across the AlTiO layer and delays the extension of the depletion region toward the p-GaN/AlGaN interface, which further increases VTH. The gate stack demonstrated a high VTH of ~4.2 V, a gate breakdown voltage of 13.6 V, and improved threshold voltage stability without compromising gate control. The physical insights further indicated that VTH can be pushed even higher by tuning the p-type properties of AlTiO, indicating promising potential for this technology in e-mode GaN power devices.

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APA

Malik, R. R., Joshi, V., Chaudhuri, R. R., Thakare, A. V., & Shrivastava, M. (2026). Achieving Ultrahigh Threshold Voltage in Enhancement-Mode AlGaN/GaN HEMTs With an AlxTiyO/p-GaN Integrated Gate Stack—Part II. IEEE Transactions on Electron Devices, 73(3), 1235–1242. https://doi.org/10.1109/TED.2026.3652534

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