Evaluation of warpage and residual stress in semiconductor chips caused by the combination of materials in packages

Abstract

In electronic packages such as BGA and LGA packages, it is very important for the reliability of packages to decrease their warpage during the manufacturing process and reduce the residual stress on the surface of the semiconductor chip at the service temperature. In this research, the authors proposed a simulation method to predict both the warpage of packages and the residual stress simultaneously. The developed technique considering initial warpage of components and the viscoelastic material properties of the die bonding adhesive and substrate made it possible to predict warpage and the stress after the die bonding process accurately. © 2012 The Japan Society of Mechanical Engineers.