A low power, area efficient implementation of AES algorithm

Abstract

Encryption is a procedure of convert readable information into encoded appearance so that it can’t be interpreted by the intruder. Paper presents the FPGA implementation of a low power, neighborhood efficient AES algorithm for encrypting data. From the results it has been experimental that the enhanced technique has reduced the power consumption and area compared to the existing methods. The implementation is done in 90 nm and 65 nm CMOS technology using Quartus for Cyclone II and Cyclone III.