Design and Implementation of PERES based 128 bit Parallel Adder using FPGA

Abstract

In this work, the parallel adder is designed using the PERES reversible logic gate with the resolution of 128 bits. The reversible logic gates have a unique property of one to one mapping between the input and output vectors. The simulation design is verified using the NI lab view tool for the resolution of 24 bits. For higher resolution designs, the HDL code is developed by making use of the Xilinx Spartan FPGA device. The HDL has several advantages like parallel processing, design compatibility, cost effective, reconfigurable, versatile language and design hierarchy. The performance of the proposed method is validated by comparing the area and power consumption with two FPGA devices.