A Cascaded H-Bridge Multilevel Inverter with Reduced Numberof Switches

Abstract

This paper presents simulation of a 5-level cascaded H-bridge multilevel inverter, with reduce the number of power switching devices in the current flow direction. The propose topology consists of a five switches with double DC sources. The analysis is designing a new topology for a single-phase cascaded multilevel H-bridge inverter (CHBMLI), with a focus on the number of power switching devices in the current flow direction.Conduction and switching losses have to be reduced to achieve higher performance operation of power electronic devices.Multilevel inverters are designed to achieve the desired voltages of output from different DC sources.A analysis of the simulated power loss values is deals with based on how the power switch reduction led to the loss decreases.