Combining Technology Mapping and Placement for Delay-Minimization in FPGA Designs

Abstract

We combine technology mapping and placement into a single procedure, M.map, for the design of RAM-based FPGA's. Iteratively, M.map maps several subnetworks of a Boolean network into a number of CLB's on the layout plane simultaneously. For every output node of the unmapped portion of the Boolean network, many ways of mapping are possible. The choice of which mapping to be used depends not only on the location of the CLB into which the output node will be mapped but also on its interconnection with those already mapped CLB's. To deal with such a complicated interaction among multiple output nodes of a Boolean network, multiple ways of mappings and multiple number of CLB's, any greedy algorithm will be insufficient. Therefore, we use a bipartite weighted matching algorithm in finding a solution that takes the global information into consideration. With the availability of the partial placement information, M.map is able to minimize the routing delay in addition to the number of CLB's. Experimental results on a set of benchmarks demonstrate that M.map is indeed effective and efficient. © 1995 IEEE