Area Efficient Computing-in-Memory Architecture Using STT/SOT Hybrid Three Level Cell

Abstract

Spintronic-based computing-in-memory (CiM) architecture has emerged as one of the efficient solutions to counter the latency/bandwidth bottleneck of conventional von-Neumann architecture. However, computation within a small area while achieving low power consumption still remains a challenge. Multi-bit spintronic storage device is a suitable solution to improve the integration density of such architectures. This paper focuses on using spin-transfer torque (STT)/spin-orbit torque (SOT) based hybrid three-level cell (TLC) in CiM application for implementing logic circuits such as AND, XOR, and magnetic full adder (MFA). Moreover, the performance of the STT/SOT-TLC-based MFA is compared with other full adder designs. The results show that the proposed MFA is 75% more area-efficient in comparison to two-bit STT and SOT-based designs, and 50% more area-efficient in comparison to differential spin hall effect (DSHE) based designs