Analysis and Suppression of High Speed Dv/Dt Induced False Turn-on in GaN HEMT Phase-Leg Topology

Abstract

Gallium nitride high electron mobility transistor (GaN HEMT) is liable to gate false turn-on problem when the gate crosstalk voltage exceeds its threshold voltage in the widely adopted phase-leg topology due to its low threshold voltage and high switching speed. Without considering the gate loop stray inductance, gate internal resistance, nonlinearity of parasitic capacitances and power loop stray parameters, traditional false turn-on analytical method is insufficient to support accurate analysis. And it has been found that GaN HEMT gate-source parasitic capacitance Cgs previously assumed constant is otherwise highly nonlinear and has strong impacts on the gate crosstalk voltage. This paper has measured Cgs by vector network analyzer and constructed an accurate nonlinear model of Cgs , based on which an accurate GaN HEMT behavior model is further fulfilled. The accuracy of the proposed behavior model has been verified by large amounts of experiment results. The proposed GaN HEMT model is used to accurately calculate gate crosstalk voltage and switching losses. Besides, false turn-on induced extra loss has been calculated and is adopted as a criterion to evaluate the severity of false turn-on and optimal design method for false turn-on suppression has been detailed further.