Implementation of Parallel BCH Encoder Employing Tree-Type Systolic Array Architecture

Abstract

A BCH (Bose-Chaudhuri and Hochquenghem) code is one of the most widely used error correcting codes for the detection and correction of random errors. This paper presents an error correction coding with a suitable BCH code for MLC (multi-level cell) flash memory. The conventional bit serial BCH code cannot adequate with the recent high speed circuit. Therefore, parallel encoding and decoding algorithms are always a necessity. We introduced a new systolic array type BCH parallel encoder and syndrome generator for decoder. The area and speed of the encoder is compared with several parallel factors. Furthermore, to prove the efficiency of the proposed algorithms using tree-type structures, the throughputs and the area overhead of the encoder and the syndrome generator were compared with their counterparts also. The proposed algorithm has a great flexibility in parallelization and the speed with tree-type structure was increased by 29% and 33% respectively. The synthesis and simulation results were implemented on FPGA using VHDL.