Implementation of a Secure 32-bit RISC-V Microcontroller Integrated With a Fast Lightweight Post-Quantum NTRU-HPS Cryptosystem for IoT

Abstract

The emergence of large-scale quantum computers threatens the long-term security of classical public-key cryptosystems, making the integration of post-quantum cryptography (PQC) essential for resource-constrained embedded and IoT platforms. To address this challenge, we propose a compact and secure RISC-V microcontroller tightly integrated with a lightweight, high-throughput NTRU-HPS-2048-509 hardware accelerator for quantum-resilient edge computing. Unlike recent PQC–RISC-V prototypes that focus only on software optimization or standalone polynomial engines, this work implements the complete NTRU KeyGen, encryption, and decryption pipeline entirely in hardware. A write-only, tamper-resistant interface ensures hardware-isolated and constant-time execution, while a precomputed Key-LUT removes runtime polynomial inversion, enabling fast and leakage-resistant key generation. A parallel circular polynomial-multiplication engine combined with LUT-optimized modular arithmetic achieves single-loop N-cycle processing, enabling ultra-low-latency NTRU execution: 2,040 cycles for KeyGen, 2,039 cycles for encryption, and 3,058 cycles for decryption—achieving speedups of over 300 times (Enc) and 540 times (Dec) compared with optimized software implementations. The proposed SoC occupies only 14,019 adaptive logic modules (ALMs) on a Cyclone V SE FPGA, of which the NTRU accelerator accounts for 11,166 ALMs. In ASIC implementation using a 45 nm CMOS process, the SoC integrates 429,628 standard cells, with the NTRU accelerator contributing 122,382 cells (about 28.5% of SoC). Importantly, the total power consumption of the entire MCU is 59.26 mW at 160 MHz, and a compact 1.925 mm2 core area. Detailed power analysis reveals that 85% of this consumption is attributed to sequential and clock network overheads caused by implementing on-chip memory as standard cell registers. By isolating the computational logic, we estimate the NTRU accelerator's active power to be approximately 17.78 mW. We demonstrate that replacing register-based storage with SRAM hard macros is projected to reduce total system power by nearly 60% (to ∼24.5 mW). The results confirm that while the accelerator logic is computationally intensive, the system's energy efficiency is sufficient for high-security IoT applications when optimized with dedicated memory macros. By combining RISC-V architectural openness with a lightweight, gate-efficient, and hardware-isolated PQC engine, this work establishes a practical, scalable blueprint for integrating lattice-based cryptography into next-generation IoT, edge-security systems.