Using a neural network-based approach to predict the wafer yield in integrated circuit manufacturing

Abstract

In integrated circuit (IC) manufacturing, defects on wafer tend to cluster. As the wafer size increases, the clustering phenomenon of the defects becomes increasingly apparent. When the conventional Poisson yield model is used, the clustered defects frequently cause erroneous results. In this study, we propose a neural network-based approach to predict the wafer yield in IC manufacturing. The proposed approach can reduce the phenomenon of the erroneous predictions caused by the clustered defects. A case study is also presented, demonstrating the effectiveness of the proposed approach. In addition, the proposed approach can be written as a computer software to accurately predict the wafer yield in IC manufacturing.