An effective approach to schedule time reduction on multi-core embedded systems

Abstract

In today's computing world, the shift towards deploying multiple processors to generate more computing power is the trend to replace single core architectures. Although multiple processing cores have the potential to enhance the computing power, it is only as effective as the tools to parallelize the applications utilizing the system. In the area of embedded systems, multiprocessor-system-on-chip (MPSoCs) adopts the idea of adding more cores to a single chip. Thanks to advances in VLSI and architecture designs, multiple processing cores, complex communication interconnections, different memory hierarchies, along with set of inputs/outputs constitute an MPSoC. An MPSoC solves the problems of increasingly complex embedded applications that need to be run fast enough without prohibitive power consumption. MPSoCs often hosts multiple embedded applications. The MPSoC is supposed to effectively execute the applications concurrently using the system under set of constraints. Constraints can be speed through deadlines or power consumption. Often researchers consider a simpler version of this scenario where one application is utilizing the system at a time. This is an over simplification of the problem that might limit its applicability in real life scenarios. In this article, we present a holistic approach to resource partitioning and task scheduling under memory awareness of multiple embedded applications on an MPSoC with the objective of reduced schedule times. Results on different benchmark combinations show that our approaches effectively reduced the schedule computation times.