Signal Integrity and Computing Performance Analysis of a Processing-In-Memory of High Bandwidth Memory (PIM-HBM) Scheme

Abstract

In this article, we propose a processing-in-memory of high bandwidth memory (PIM-HBM) scheme including system architecture and hardware structure. The proposed scheme embeds processing units into the logic layer of the high bandwidth memory (HBM) to expose an excess dynamic random access memory (DRAM) bandwidth. With parallelized DRAM architecture and a high-speed through-silicon via (TSV) structure, the proposed scheme successfully extends the DRAM bandwidth of processing-in-memory (PIM). Also, the total energy consumption is decreased by the reduced interconnection and capacitance-reduced channel structure. We designed the overall architecture and structure with physical feasibility for application to the current HBM. The logic layer and DRAM layers in the HBM are configured to embed the processing units and parallelize the DRAM channels. For high-speed data transfer with low interconnect energy, the TSV and silicon interposer channels are designed and analyzed in consideration of signal integrity (SI). Based on the physical design, we obtained the interconnect length in detail. The interconnect energy and delay of the silicon interposer and on-chip interconnect were modeled through a SPICE simulation. We analyzed the accurate effects of interconnect reduction caused by PIM. For overall system performance and efficiency analysis, a cycle-level architectural simulation was conducted. We successfully evaluated and analyzed the system performance for memory-intensive applications. As a result, the proposed PIM-HBM achieves 53% and 10.4% improvement on average in computing performance and energy efficiency compared to the conventional graphic processing unit of high bandwidth memory (GPU-HBM).