Microstrip impedance management through multilayer PCB stack-up: Discontinuity compensation voids with asymmetric dielectrics

Abstract

To process high-frequency signals on a printed circuit board (PCB), it is often necessary to carefully analyze and select the pad widths of the chip packages and components to match their impedance to the standard Z0. Modern PCBs are complex multilayer designs, utilizing either only high-end laminates, low-end laminates, or a combination of both. The on-board component footprints usually have larger pads that become discontinuities and corrupt the impedance of critical traces. One way to address this issue is to include reference plane cutouts as a measure of compensation. This paper aims to find out how an asymmetric dielectric stack-up affects the microstrip discontinuity impedance compensation using reference plane cutouts. The selected board layer stack-up imitates several different practical design scenarios, including costly PCBs that strictly comprise high-end dielectric materials, as well as trying to lower PCB cost by introducing low-cost materials without major performance sacrifice. S-parameter measurements are performed and confirmed by time domain reflectometry (TDR) measurements.