Execution of Median Filter Built on FPGA for Trimming Noise Meeting the Real Time Requirements

Abstract

As images plays a vital in all aspects, there is a need to met the real time requirements in processing the image. Major challenges raised in processing the image is noise. The utmost typical difficult is effective denoising creation as well as quick functioning in the processing of digital image noise suppression process for the need of real time consequences to afford image with high quality this project was introduced. Generally filters plays a major role to remove the impulse noise in acquired images. The filter named sliding window spatial filter which is familiar as median filter is effective technique to eradicate impulse noise from the devoleped image. But in real time, it is very difficult to execute. To overcome this, FPGA methodology is introduced to fulfills the support besides the optimization of major constraints like area, speed, power. In addition to this, it assures technical sustenance of eradicating noise in image as per requirements in real time. Regarding the design and structure appearances in FPGA, Xilinx software is used for simulation and code has been written in Verilog language.