A Guide for Accurate and Repeatable Measurement of the RTH,JC of SiC Packages

Abstract

This work aims to understand the influence of various test conditions on the measurement of the junction-to-case thermal resistance (RTH,JC) of SiC packages, and identify a procedure that will result in accurate and repeatable measurements. In this study, the RTH,JC measurements of a PCB-embedded half-bridge package containing silicon carbide (SiC) MOSFETs under different test conditions are evaluated. The RTH,JC is determined using the transient dual interface method (TDIM), as reported in the JEDEC JESD51-14 standard. The thermal conductivity of the thermal grease was found to have an impact on repeatability of RTH,JC measurements. RTH,JC measurement sets resulting from alternative copper standoff thickness, negative gate bias, thermal grease thickness, and clamp tip style were found to have statistically significant differences in RTH,JC measurement mean compared to the control set. A method for reducing deviation in RTH,JC measurements is proposed. The RTH,JC of a TO-247 package containing the same SiC MOSFET die is reported to act as a commercially available reference for the PCB-embedded package.