Design of FPGA based 32-bit Floating Point Arithmetic Unit and verification of its VHDL code using MATLAB

Abstract

Most of the algorithms implemented in FPGAs used to be fixed - point. Floating - point operations are useful for computations involving large dynamic range, but they require signifi cantly more resources than integer operations. With the c urrent trends in system requirements and available FPGAs , floating - point implementations are becoming more common and d esigners are increasingly taking advantage of FPGAs as a platform for floating - p oint implementations. The rapid advance in Field - Programmable Gate Array (FPGA) technology makes such devices increasingly attractive for implementing floating - point arithmetic. Compared to A pplication S pecific I ntegrated C ircuits, FPGAs offer reduced deve lopment time and costs . Moreover, t heir flexibility enables field upgrade and adaptation of hardware to run - time conditions. A 32 bit floating point arithmetic unit with IEEE 754 Standard has been designed using VHDL code and all operations of addition, su btraction, multiplication and division are tested on Xilinx. Thereafter, Simulink model in MAT lab has been created for verification of VHDL code of that Floating Point Arithmetic Unit in Modelsim .