Systematic design of a 14-bit 150-MS/s CMOS current-steering D/A converter

Abstract

This paper presents a D/A converter with a 14-bit intrinsic linearity in 0.5μm CMOS technology, which has been designed using a systematic design methodology for current-steering D/A converters. A flexible architecture is proposed for which the design parameters are calculated using a performance-driven top-down design methodology. The layout of the regular structures typical for D/A converters is automatically generated. Measurement results are reported. Due to the systematic design methodology, the design was realized in less than one month total accumulated person effort.