Regular layout generation of logically optimized datapaths

Abstract

The inherent distortion of the structural regularity of VLSI datapaths after logic optimization has until now precluded dense regular layouts of optimized datapaths despite their implicit regularity. This paper presents a methodology enabling utilization of datapath regularity for dense layout even after extensive logic optimization. A structural netlist analysis extracts regularity from the initial unoptimized netlist which serves as a partial relative regular preplacement. After each customary iteration of placement, backannotation and logic optimization, functional correspondences between the optimized and the original netlists are identified by a logic correspondence extractor. The functional and structural analyses results are then merged yielding a regular preplacement for the logically optimized design.