A two-result-per-cycle deblocking filter architecture for QFHD H.264/AVC decoder

Abstract

We propose a high-performance hardwired deblocking filter for H.264/AVC decoding. To decode QFHD (3840 × 2160, i.e., four times full HD) ultra high definition video, we minimize number of processing cycles, working frequency and amount of external memory traffic. We propose a novel filtering order and employ a 5-stage pipelined and resource-shared dual-edge filter to generate two filtering results every cycle. Taking advantage of skip modes, our filter takes only 48 cycles to filter a macroblock in the best case and 100 in the worst case. Furthermore, it eliminates most unnecessary off-chip memory traffic with a novel on-chip memory scheme. Our design can support QFHD at 30 fps application by running only at 98 MHz. © 2009 IEEE.