Single-grain gate-all-around si nanowire FET using low-thermal-budget processes for monolithic three-dimensional integrated circuits

Abstract

We introduce a single-grain gate-all-around (GAA) Si nanowire (NW) FET using the locationcontrolled-grain technique and several innovative low-thermal budget processes, including green nanosecondlaser crystallization, far-infraredlaser annealing, andhybridlaser-assistedsalicidation, thatkeep the substrate temperature (Tsub) lower than 400 °C formonolithic three-dimensional integrated circuits (3D-ICs). The detailed process verification of a low-defect GAA nanowire and electrical characteristics were investigated in this article. The GAA Si NWFETs, which were intentionally fabricated within the controlled Si grain, exhibit a steeper subthreshold swing (S.S.) of about 65mV/dec., higher driving currents of 327 μA/μm (n-type) and 297 μA/μm (p-type) @ Vth 0.8 V, and higher Ion/Ioff (>105 @|Vd| = 1 V) and have a narrower electrical property distribution. In addition, the proposed Si NW FETs with a GAA structure were found to be less sensitive to Vth roll-off and S.S. degradation compared to the omega(Ω)-gate Si FETs. It enables ultrahigh-density sequentially stackable integrated circuits with superior performance and low power consumption for future mobile and neuromorphic applications.