Determination of Thermal Induced Stresses in Semiconductor Chip Package by using Finite Element Analysis: A Brief Review

Abstract

In todays advanced electrical technology, it becomes necessity to use compact semiconductor chips in variety of areas like computers, electrical appliances, automotive etc., clearly the need of more and more sophisticated packages is increasing. As the need of faster computer increases design of denser and more complicated packages becomes unavoidable, more complicated packages means that, the size of chip more or less remains same, but it has more electronic circuitry per unit surface area, this, of course increases the temperature of packages and causes thermal expansion due to change in coefficient of thermal expansion of the constituent materials. Thermal stresses ultimately cause the failure of the device. An IC package mainly consist of four parts, silicon die (chip), polymeric substrate, plastic molding compound and connectivity parts, lead frames and bond wires. The silicon chip is assembled on a polymeric substrate, plastic molding compound surrounding both parts, lead frames and bond wires provide electrical connectivity between the package and board on which assembly is made. The complicated geometrical structure and different material properties as well as the loading conditions made it almost impossible to study the mechanical behavior of semiconductor package analytically; therefore the finite element method has become a useful tool for evaluation of problems encountered in this area.