Memory repair by die stacking with through silicon vias

Abstract

As we adopt more advanced process technologies, the volume production of memory devices, such as DRAM and Flash, becomes more difficult. It seems inevitable that during the ramp-up period, the initial manufacturing yield will be lower, and it takes more time and effort to improve the yield to a reasonable level. Although redundancy can be used to improve the yield eventually, the reserved spares may not be enough at the beginning, so most dies may be irreparable. We propose the usage of three-dimensional (3D) integration to achieve yield enhancement. Through silicon vias (TSVs) patch good memory blocks in a bad die with those in another bad die by bonding them together and enabling the built-in circuit. The die stack has the same functionality, though slightly increases delay and power. Nevertheless, if the production yield takes a long time to achieve, the 3D patched memory is deemed to be a transitional-period product. It does help to shorten time-to-market and make the irreparable memories profitable. © 2009 IEEE.