Eightdirectional smart reconfigurable router design for network on chip (Noc)

Abstract

Designing N.O.C routers are based on performance parameters like power dissipation, energy, latency[2].These performance are usually defined during design time.Taking under consideration all parameters as buffer size while designing lead to higher side of power dissipation and higher latency. Large size buffers lead to good performance but at the same time cause excess power dissipation. In this paper our aim is to design a router which supports heterogeneous data.