Source/drain junctions and contacts for 45 nm CMOS and beyond

Abstract

One of the greatest challenges for future CMOS generations is to limit the series resistance of source/drain junctions and their contacts to a small fraction of the channel 'on' resistance. This challenge is paused by structural changes in transistor design as well as fundamental limitations of silicon as a semiconductor. It is anticipated that junctions that rely solely on ion-implantation combined with an advanced annealing technique will not meet our expectations beyond the 45 nm node. Fundamentally different processes and new materials are needed to meet the future requirements. Starting with the 90 nm technology node, we have already begun to see examples of departures from the conventional junction formation methods. A good example is Intel's 90 nm technology process featuring recessed Si 1-xGe xsource/drain junctions incorporated to address the series resistance concerns and to introduce uniaxial strain into the channel for enhanced mobility. It is predicted that within a few years the conventional planar MOSFET will be replaced with one of the so-called "non-classical" transistor structures, which include the fully-depleted SOI, FINFET and various structures proposed for enhanced carrier mobility via strain engineering. Unfortunately, these structures bring their own source/drain integration challenges requiring further innovations in materials and processes. This paper presents an overview of the key source/drain challenges with emphasis on MOSFET series resistance. Potential solutions to these challenges with emphasis on applications of Si 1-xGe xin source/drain engineering will be discussed in reference to various transistor structures currently considered as potential candidates for future CMOS generations. © 2005 American Institute of Physics.